FIG. 1 is a block diagram illustrating a conventional multiplier circuit 100 which performs one 18-bit multiplication or two 9-bit multiplications. Multiplier circuit 100 includes input ports 101 and 102, 18-bit multiplier 110, 9-bit multipliers 120 and 121, multiplexer 130 and output port 103. Eighteen-bit words A[17:0] and B[17:0] are provided to multiplier circuit 100 at input ports 101 and 102, respectively. Eighteen-bit word A[17:0] consists of a 9-bit upper byte A[17:9] and a 9-bit lower byte A[8:0]. Similarly, 18-bit word B[17:0] consists of a 9-bit upper byte B[17:9] and a 9-bit lower byte B[8:0].
To perform an 18-bit multiplication, 18-bit words A[17:0] and B[17:0] are provided to 18-bit multiplier 110. 18-bit multiplier 110 is a conventional device which contains at least four 9-bit multipliers similar to 9-bit multipliers 120 and 121. The output signal of 18-bit multiplier 110 is a 36-bit (in parallel) word output signal which is equal to the product of A[17:0] and B[17:0]. A multiplexer select signal on lead 131 causes multiplexer 130 to route the 36 output bits of 18-bit multiplier 110 to output port 103.
Multiplier circuit 100 is also capable of performing two 9-bit multiplications. To do this, 9-bit upper byte A[17:9] is multiplied by 9-bit upper byte B[17:9] to form a first 18-bit product and 9-bit lower byte A[18:0] is multiplied by 9-bit lower byte B[8:0] to form a second 18-bit product. Thus, 18-bit word A[17:0] is separated into two 9-bit bytes A[17:9] and A[8:0] at port 150. Nine-bit byte A[17:9] is provided to an input bus of multiplier 120 and 9-bit byte A[8:0] is provided to an input bus of multiplier 121. Similarly, 18-bit word B[17:0] is separated into two 9-bit bytes B[17:9] and B[8:0] at port 151. Nine-bit byte B[17:9] is provided to an input bus of multiplier 120 and 9-bit byte B[8:0] is provided to an input bus of multiplier circuit 121.
Nine-bit multiplier 120 is a conventional multiplier circuit which produces an 18-bit word equal to A[17:9]*B[17:9]. Nine-bit multiplier 121 is typically identical to 9-bit multiplier 120. Thus, the output signal of 9-bit multiplier 121 is equal to A[8:0]*B[8:0]. The output signals of multipliers 120 and 121 are concatenated at port 152, resulting in a 36-bit output signal. The upper half of this 36-bit output signal is equal to the product of A[17:9] and B[17:9] and the lower half of this 36-bit output signal is equal to the product of A[8:0] and B[8:0]. Consequently, the two 9-bit multiplications previously described have been performed. A multiplexer select signal on lead 131 causes multiplexer 130 to route the 36-bit output signal of concatenation port 152 to output port 103.
Because multiplier circuit 100 requires an 18-bit multiplier 110, two 9-bit multipliers 120 and 121, and multiplexer 130, the area required to fabricate multiplier circuit 100 is significant. Because of the desire to minimize the layout area of integrated circuits, it would be advantageous to have a multiplier circuit with a reduced area which is capable of selectably performing either a large multiplication or two small multiplications.